Dynamically reconfigurable computing platforms provide promising methods for dynamic management of hardware resources,\npower, and performance. Yet, progress in dynamically reconfigurable computing is fundamentally limited by the reconfiguration\ntime overhead. Prior research in the development of dynamic partial reconfiguration (DPR) controllers has been limited by its use\nof the Processor Local Bus (PLB). As a result, the bus was unavailable during DPR. This resulted in significant time overhead.\nTo minimize the overhead, we introduce the use of a multiport memory controller (MPMC) that frees the PLB during the\nreconfiguration process. The processor is thus allowed to switch to other tasks during the reconfiguration operation. This effectively\nlimits the reconfiguration overhead. An interrupt is used to inform the processor when the operation is complete. Therefore, the\nsystem can multitask during the reconfiguration operation. Furthermore, to maximize performance, we introduce the use of\noverclocking with active feedback. During overclocking, the use of active feedback is used to ensure that the device voltage and\ntemperature are within nominal operating conditions. All of these contributions lead to significant performance improvements\nover current partial reconfiguration subsystems. The portability of the system, demonstrated on the Virtex-4 and the Virtex-5,\nconsists of four different hardware platforms.
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